1. Field of the Invention
This invention is related to an improved method of repairing high density interconnect (HDI) circuits and, more particularly, is directed to an improved method for gaining access to, for the purpose of replacing, a defective integrated circuit chip situated in a high density interconnect circuit, the improved method being simpler and less damaging than previous methods of repairing HDI circuits.
2. Description of the Prior Art
HDI circuits are comprised of a plurality of integrated circuit chips mounted on a substrate where the chips are interconnected by a metallization pattern created on a polymer overlay layer. In some HDI circuits, a multilayer interconnect pattern is formed over the chips and is comprised of a multiplicity of polymer overlay layers with each layer having its own interconnect pattern formed thereon. Typically, the interconnect pattern is formed by a computer-controlled laser lithography system. The above-referenced co-pending patent applications describe and illustrate these circuits in detail.
An important objective of HDI circuit technology is to provide the ability to gain clear access to any defective integrated circuit chip contained in the HDI circuit, so as to have the ability to replace such chip without damaging or contaminating the HDI circuit. This necessitates having capability to remove the polymer overlay layer and replace it with a new polymer overlay layer without damage to the chips below. In the above-referenced co-pending patent application Ser. No. 912,456, now U.S. Pat. No. 4,783,695 issued Nov. 8, 1988 a batch process for removing multiple layers of polymer overlays is described. This batch process includes etching or dissolving the metallization pattern, followed by etching or dissolving the polymer layer. For multilayer interconnects, this process is cyclically repeated until only the first-applied polymer layer and interconnect pattern formed thereover remains. The copper layer of the interconnect metallization is then removed by dissolving it in a bath of nitric acid, sulfuric acid, and phosphoric acid. The titanium layer of the interconnect metallization is then removed by reactive ion etching (RIE) in gaseous CF.sub.4. After the titanium is cleaned from the integrated circuit chip pads, the RIE plasma gas is changed to oxygen enhanced by CF.sub.4 and the polymer overlay layer, preferably Kapton.RTM. polyimide film available from E.I. du Pont de Nemours and Company of Wilmington, Delaware, and the bonding adhesive, usually Ultem.RTM. thermoplastic resin available from General Electric Company, Pittsfield, Massachusetts, are etched. The process yields a substrate with bare, clean chips mounted thereon and ready for reprocessing. In the above-referenced co-pending patent application Ser. No. 230,654, another batch process for removing a polymer overlay layer is described. The latter batch process includes dissolving the copper metallization with a mixture of nitric acid, sulfuric acid, and phosphoric acid, dissolving the titanium metallization with fluoroboric acid, and removing the overlay polymer and adhesive by immersion in tetrahydrofuran (THF). As an alternative, methylene chloride can be used to lift off the polymer overlay layer after the metallization has been dissolved, as stated in the above-referenced co-pending patent application Ser. No. 230,654.
Several drawbacks to using the removal methods described above have been encountered. One is that no completely selective etch for titanium over aluminum is available. Therefore, the aluminum pad of an integrated circuit chip is at risk during the titanium etch. Repeated repairs could result in the pad area being attacked and the chip ultimately becoming inoperative. A second drawback relates to the chip being vulnerable to scratches. Kapton polyimide film is a very tough material and a loosened, floating Kapton overlay layer could slide against the top of the chip and scratch the surface. Although the adhesive layer which holds the overlay layer on the tops of the chips may provide some protection against scratching, this protection can be lost if the substrate is left in the solvent long enough for it all to be dissolved. A third drawback stems from the repetition required to remove multilayer interconnect patterns. The reason for employing a cycling procedure is due to the fact that dielectric materials act as a stopper for removal of metallization, and metallization acts as a stopper for dielectric removal. Nevertheless, removal of metallization followed by removal of a dielectric layer in a repeating cycle adds complexity to the overall repair process. A fourth drawback is encountered when a repair is attempted on circuits that use a metal other than copper on the layers above the first (i.e., lowermost) layer. For example, in circuits where the upper layer of metal is connected to wire bonding which, in turn, is connected to the package pins, the metal layer of choice is aluminum or gold. When etching aluminum during the repair process, there is a risk that the aluminum pad on an integrated circuit chip will be exposed to the etchant and be damaged. Use of gold does not avoid this risk since gold etchants generally attack aluminum as well.